The Functional testing of any device, digital or analog, includes the steps of functional verification and characterization. In the design of a new integrated circuit (IC) such as a computer processor, functional characterization is performed on Primary Input and Output logic in the chip itself in order to verify the timing. Modern, complex IC devices are designed to contain one or more embedded core data processors for processing digital signals such as computer instructions from internal or external software. The core is operatively communicates with memory, peripherals, and other circuitry in the IC. An embedded core of an IC also has many input and output terminals, many of which are not directly accessible by the external pins of the IC. Thus, there is no direct access to these I/Os for characterization and testing.
Two types of tests, scan vector test and application vector test, are used to verify function parameters of a device. The scan vector test, also called a structural test, used in scan chain and boundary scan configurations, is used to search for defects and verify logical or physical failures within a circuit. Application vector testing is used to verify that a circuit is functional, the circuit is correctly controlled by primary inputs, and that the expected protocols and behaviors are observed in the primary outputs and primary inputs. When an IC is designed, the logic paths and functions are characterized according to design protocols to make sure the chip works correctly. Vector patterns are used to send instructions into the chip's inputs in order to create outputs.
Logic that is built into a an integrated circuit (IC) in order to facilitate characterization and testing of the chip is called “Design for Test” (DFT). DFTs for functional testing are a necessary step to perform on a new processor design to insure that the logical functions designed in the processor perform properly. Characterization determines timings of the device to define exactly the way the actual manufactured device works. Characterization is verifying the input/output (I/O) timing of the IC on all split lot materials and operating conditions. Usually characterization is performed, by using complex functional tests of the device. DFT logic facilitates this process.
FIG. 1 illustrates a simplified circuit diagram containing sequential logic elements connected to logic blocks. Each logic element is a flip-flop (“FF”), which is a logic circuit that can hold one bit of memory with data input and output. The output is driven by a clock, and the output changes in synchronization with the clock cycle. Each D-type flip-flop has a single input in addition to a clock and stores a single bit of data, either a zero (0) or a one (1). For example, a D flip-flop will transfer data from a D input to Q output pin on the rising edge of the clock (rising edge triggered FF). A set of D flip-flops operably connected by data input and outputs all run with a common clock or different clocks. In circuit 10, inputs 12 comprises input data according to the data sheet that is transmitted to logic block 14. The data passes through FFs 16 before being inputted into logic block 18. Data from logic block 18 the pass through FFs 20 and third logic block 22 before being output at 24.
An inherent problem with convention methods for characterization is that up to thousands of I/Os must be characterized in an integrated circuit. In prior methods, characterization of a device was performed using very complex functional test vectors that were generated by design engineers. The functional test vectors create exact I/O transitions for timing measurements at all process corners and operating conditions, such as voltages and temperatures. Further, test engineers must create millions of complex and long functional test vectors, in order to generate the required protocol transitions at the I/Os of the IC, expending months worth of time de-bugging and operating the vectors, which can cause significant time delays to bring a new IC device to market.